There is a problem that a bit error (bit inversion or bit garbled) is caused in data which are written into a storage apparatus (semiconductor memory, hard disk apparatus or the like) and which are composed of ‘0’ and ‘1’. The bit error is a phenomenon that a datum which is ‘0’ in reality is stored as ‘1’, and in contrast a datum which is ‘1’ in reality is stored as ‘0’.
The various methods have been proposed as a method for detecting the bit error and a method for correcting the detected bit error. As an example, the method using the ECC (Error Check and Correction) code is exemplified.
Here, the reference literature 1 (Japanese Patent Application Laid-Open Publication No. 2006-260139) discloses an art that a plurality of processing apparatuses cooperatively carry out detection of the bit error by using the ECC code.